The present invention relates to methods of forming semiconductor devices and, more particularly, to forming non-volatile memory devices having floating gates.
Semiconductor memory devices for storing data can be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data upon interruption of their power supplies. In contrast, nonvolatile memory devices retain their stored data after interruption of their power supplies. Flash memory devices are an exemplary type of nonvolatile memory devices. A unit cell is used to store data in a flash memory device and may include a floating gate and a control gate electrode that controls inflow/outflow of charges to/from the floating gate. An Oxide-Nitride-Oxide (ONO) layer may be used as an insulation layer between the floating gate and the control gate electrode. Peripheral circuits can include MOS transistors, where use of an ONO in gate electrodes of the MOS transistors in the peripheral circuits may degrade their characteristics.
A method of forming flash memory devices in which a gate electrode included in a MOS transistor of peripheral circuits does not include an ONO layer is disclosed in U.S. Pat. No. 6,372,577 (“the '577 patent”).
FIGS. 1 through 4 are cross-sectional views that illustrate a conventional method of forming a flash memory device. The reference sign “a” indicates a cell region with a flash memory cell, and the reference sign “b” indicates a peripheral region with a MOS transistor of a peripheral circuit.
With reference to FIG. 1, device isolation layers 2a and 2b are formed on a substrate 1 having a cell region a and peripheral regions b. The first device isolation layer 2a is formed at the cell region “a” to define a cell active region, and the second device isolation layer 2b is formed in the peripheral region “b” to define a peripheral active region.
A tunnel oxide layer 3 and a first polysilicon layer 4 are sequentially formed on an entire surface of the substrate 1. The first polysilicon layer 4 is patterned to form a first polysilicon pattern 4a on the cell active region. At this time, the first silicon layer 4 of the peripheral region “b” may remain.
An ONO layer 5 is formed on an entire surface of the substrate 1, and a photoresist pattern 6 is formed on the ONO layer 5. The photoresist pattern covers the ONO layer 5 of the cell region “a”. At this time, the ONO layer 5 of the peripheral region “b” is exposed.
With reference to FIG. 2, the ONO layer 5 of the peripheral region “b” and the first polysilicon layer 4 are removed using the photoresist pattern 6 as an etch mask. Accordingly, the peripheral active region is exposed. The photoresist pattern 6 is removed to expose the ONO layer 5 of the cell region “a”.
A pre-cleaning process is performed on a surface of the exposed peripheral active region. A gate oxide layer 7 is formed in the peripheral active region. The gate oxide layer 7 is formed by a thermal oxidation process.
With reference to FIG. 3, a second polysilicon layer 8 is formed on an entire surface of the substrate 1. The second polysilicon layer 8 of the cell region “a” is in contact with the ONO layer 5, and the second polysilicon layer 8 of the peripheral region “b” is in contact with the gate oxide layer 7.
With reference to FIG. 4, the second polysilicon layer 8, the ONO layer 5, and a first polysilicon pattern 4a are successively patterned to form a floating gate 4b, the ONO pattern 5a, and a control gate electrode 8a, which are sequentially stacked. The control gate electrode 8a crosses over the cell active region. The floating gate 4b is interposed between the control gate electrode 8a and the cell active region. The second polysilicon layer 8 of the peripheral region “b” is patterned to form a peripheral gate electrode 8b crossing over the peripheral active region. In FIGS. 1-4, the cross-section of the cell region “a” is taken along line of the control gate electrode 8a. 
As explained above, the ONO layer 5 of the peripheral region “b” is removed by a patterning process using the photoresist pattern 6. The ONO layer 5 of the cell region “a” directly contacts the photoresist pattern 6 during the removal of the ONO layer 5 of the peripheral region “b”. Because photoresists are typically formed from organic materials, the ONO layer 5 of the cell region “a” may obtain organic contamination from the photoresist pattern 6 and may thereby have degraded characteristics, and which may reduce reliability of a flash memory device made therewith.
Additionally, during the pre-cleaning process before forming the gate oxide layer 7, the ONO layer 5 of the cell region “a” is exposed and may be partially removed and damaged during the pre-cleaning process. As a result, the characteristic of the ONO layer 5 of the cell region “a” may be degraded and/or the thickness of the ONO layer 5 of the cell region “a” may vary across a flash memory device and/or between manufacturing cycles.
The ONO layer 5 of the cell region “a” is also exposed during an oxidation process for forming the gate oxide layer 7, which may make it difficult to control the thickness of the ONO layer 5.
Accordingly, the reliability of such flash memory devices may be reduced.